In the fabrication of integrated circuits, various layers, e.g., conductive layers and insulative layers, are used. For example, during the formation of semiconductor devices, such as dynamic random access memories (DRAMs), insulating layers are used to electrically separate conductive layers such as doped polycrystalline silicon, aluminum, metal silicides, etc. It is often required that the conductive layers be interconnected through holes or openings in the insulating layer. Such holes are commonly referred to as contact holes, e.g., when the hole extends through an insulating layer to an active device area, or vias, e.g., when the hole extends through an insulating layer between two conductive layers. The profile of an opening is of particular importance such that specific characteristics can be achieved when a contact hole or via is provided or filled with one or more conductive materials, e.g., conductive barrier layers.
Conductive materials are also formed in openings when providing certain storage cell capacitors for use in semiconductor devices, e.g., DRAMs. Storage capacity and size are important characteristics of a storage cell. Generally, a storage cell capacitor is formed with a dielectric constant material interposed between two conductive electrodes. One or more layers of various conductive materials may be used as the electrode material. For example, one or more Group VIII metals, such as rhodium or platinum, may be used for the electrode material.
Many storage cell capacitors are formed by processes including high aspect ratio openings. For example, container-type capacitors are described in U.S. Pat. No. 5,392,189 to Fazan, et al., entitled “Capacitor Compatible With High Dielectric Constant Materials Having Two Independent Insulative Layers and the Method for Forming Same,” issued Feb. 21, 1995, and also in U.S. Pat. No. 5,270,241 to Dennison, et al., entitled “Optimized Container Stacked Capacitor DRAM Cell Utilizing Sacrificial Oxide Deposition and Chemical Mechanical Polishing,” issued 14, Dec. 1993. In such references, methods for forming container-type cell capacitor structures are described which generally include the formation of an insulative layer over existing topography and then etching openings into the insulative layer allowing access to the underlying topography, e.g., for a cell capacitor, the underlying topography may include conductive regions (e.g., conductive plugs). Thereafter, a conductive layer (e.g., polysilicon) to be used for forming the bottom electrode of the cell capacitor is formed within the openings, e.g., on the bottom surface and side walls of the openings, and is also formed on the upper surface of the insulative layer in which the opening has been defined. In one illustrative process described in the references, a layer of oxide material is formed over the polysilicon to a thickness enough to completely fill the polysilicon-lined openings. Thereafter, this oxide material is removed down to the polysilicon, preferably by chemical mechanical planarization (CMP) which selectively stops on the upper exposed regions of the polysilicon. Thereafter, the upper portions of the polysilicon are removed to separate neighboring polysilicon structures, thereby forming individual containers (e.g., contact openings lined with the polysilicon and filled with oxide material) and exposed insulative material between such containers. Thereafter, the oxide material still filling the opening over the polysilicon is removed, leaving the opening lined with a polysilicon bottom electrode for use in forming the container-type cell capacitor.
Storage capacity and size are important characteristics in a storage cell. One way to retain the storage capacity of a device and decrease its size is to increase the dielectric constant of the dielectric layer of the storage cell capacitor. Therefore, preferably a high dielectric constant material is used in applications interposed between two electrodes. Group VIII metals such as platinum, rhodium, iridium, ruthenium, and osmium, also sometimes referred to as noble metals, are desirable electrode materials for such high dielectric constant capacitors. Therefore, it is desirable to form the Group VIII metals or their alloys in openings as described above.
However, Group VIII metals, such as platinum or platinum alloys such as platinum-rhodium, are not easily planarized. For example, an illustrative planarization problem associated with the use of a Group VIII metal is shown in FIG. 1A. FIG. 1A shows a substrate assembly 10 including a lower portion 11 and an insulative layer 12 formed thereon. An opening 15 is defined in the insulative layer 12 to the lower portion 11 of the substrate assembly 10. To form a lower electrode or bottom electrode of a container-type capacitor structure, a Group VIII metal layer 13, such as platinum, is formed over the insulative layer and as a lining in opening 15. A photoresist layer 14 is formed over the Group VIII metal layer 13 to completely fill the opening 15. Upon planarization, the upper region of layer 14 is removed along with the Group VIII metal portion 13 outside of opening 15, resulting in the non-dashed lining 17. However, problematically, the Group VIII metal, such as platinum, is deformed at the upper region of the opening 15. As shown in FIG. 1A, the platinum material is pushed into the center of the container opening 15 as represented by the projections 16 during planarization. Such deformation of the platinum layer in the container opening 15 produces an undesirable profile and is further problematic for removing the resist 14 from within the opening 15. In addition, the platinum material can be smeared across the entire container making it difficult to complete the formation of a container capacitor.
As shown in FIG. 1B, a method of using a Group VIII metal layer is shown wherein the metal layer 23 is not planarized but rather etched. For example, as shown in FIG. 1B, the substrate assembly 20 includes a lower portion 21 having insulative layer 22 formed thereover. An opening 25 is defined in the insulative layer 22 with a Group VIII metal layer 23 formed over the insulative layer 22 and conformally lining the opening 25. Thereafter, photoresist material 24 is formed over the structure and within the opening 25. However, as opposed to planarizing the photoresist material 24 and the metal layer 23 to the upper surface of the insulative layer 22, planarization is only used to remove the resist material to the upper surface of the metal layer 23. Thereafter, an etch is used to remove the Group VIII metal layer 23, e.g., a platinum layer. However, upon wet etching the platinum material 23 back to the insulative layer 22, the resist material 24 is pulled back away from the platinum conductive layer 23 allowing for undesirable removal of portions of the platinum as shown by the undesirably etched regions 26 in FIG. 1B.
As described above, planarization problems are clearly apparent in the formation of Group VIII metal layers within openings, e.g., formation of bottom electrodes of container-type cell capacitor structures. Such problems are also applicable when forming conductive layers within openings for other applications, e.g., contact applications, via structures, etc.